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Evidence report · Semiconductor analysis

The 4F² DRAM Cell: How Memory Is Being Redesigned for the AI Era

Evidence report: how a DRAM cell stores a bit, what moving from 6F² to 4F² changes, and what it means for AI systems. 39 sources.

Industry
Semiconductors
Region
Global
Focus
DRAM cell architecture and memory for AI systems
33.3%
less nominal cell area, from 6F² to 4F²
1.5×
the cells in the same array area, at the same F
64 ms
within which every DRAM cell is rewritten [2]
39
sources: papers, standards, patents and company statements

Evidence report. Diagrams are schematics, not any maker's layout. Area and density figures are idealised geometry unless a source is cited. Company figures are company-reported and have not been independently verified. Sources were read on 13 October 2026; most IEEE papers were read as abstracts.

Challenge

For many AI workloads the limiting resource is memory, not arithmetic. Peak server compute has grown about 3.0× every two years while DRAM bandwidth has grown about 1.6× [31], and a model that does not fit in memory does not run. That memory is DRAM, and since the early 2010s it has been built on one cell layout, known as 6F² [15, 7]. The layout is near its limit [8]. In October 2026 CXMT became the latest maker to describe a move to a smaller cell, 4F², in a conference talk reported by the trade press [37, 38]. Samsung, SK hynix, and Kioxia with Nanya have published their own versions in peer-reviewed venues [12, 14, 16]. Headlines turned the geometry into a promise of 50% more memory. The engineering says something more careful.

Solution

This report explains the cell from first principles, then tests the claims made about it. It covers how one transistor and one capacitor hold a bit [1], how the bit is read and rewritten [3], why a 4F² footprint needs a transistor that stands upright [10], what has to change in patterning, capacitors and wafer bonding to build one [22, 19, 14], and where DRAM sits among the memories of an AI server [28, 29]. Every statement is tied to a peer-reviewed paper, a standard, a patent or a named company statement, and is labelled for the kind of evidence it is.

Approach

  1. 1

    Sources first. Peer-reviewed papers, JEDEC standards and patents carry the physics. Company statements are used only for what the company said, and are labelled company-reported.

  2. 2

    Geometry is kept apart from product. A cell-area ratio is arithmetic. A capacity, a yield or a ship date is a claim that needs its own evidence.

  3. 3

    Every diagram is a schematic. None reproduces a maker's layout, and the idealised models are marked as models.

  4. 4

    Where Algorythmos fits: we do not design memory chips. We size, deploy and monitor AI systems, and memory capacity and bandwidth are inputs to that work.

One transistor, one capacitor: how DRAM stores a bit

The job: Hold one bit as electric charge, and give it back on request.

How it works

A DRAM cell is a single transistor and a single capacitor, the arrangement Robert Dennard patented for IBM in 1968 [1]. The capacitor is charged through the transistor to store the bit [1]. To read it, the bitline is first set to half the supply voltage; then the wordline opens the transistor and the charge spreads onto the bitline [2, 3]. The bitline's capacitance is about ten times the cell's, so the bitline moves by only a few per cent of the supply voltage [4]. A sense amplifier detects that small shift and drives the bitline to a full level, which also refills the capacitor [3]. The read destroys the stored value, and the amplifier puts it back [1, 4].

Limits and open problems

Charge leaks away, so every cell has to be rewritten periodically. The interval has stayed at 64 ms across several DRAM generations [2]. A smaller cell must still hold enough charge to be sensed, and keeping capacitance near 25 fF per cell gets harder as cells shrink [19].

Reading one bit, and putting it back

Reading a DRAM cell disturbs it, so every read ends with a rewrite. Schematic of one cell, not any maker's circuit.

  1. 1The capacitor holds a small charge: that charge is the bit.
  2. 2The bitline is set to a level halfway between a 0 and a 1.
  3. 3The wordline switches the transistor on.
  4. 4The charge spreads onto the much larger bitline and nudges it slightly up or down.
  5. 5The sense amplifier detects the nudge and drives the bitline to a full 0 or 1.
  6. 6That full level flows back through the open switch and refills the capacitor.

The array and the circuits around it

The job: Find one cell among billions, read it, and leave every other cell intact.

How it works

Cells sit where wordlines cross bitlines. Selecting a wordline opens a whole row, and a sense amplifier on each bitline reads and restores every cell in that row [3]. Each sense amplifier is around a hundred times the size of a cell, so cells are grouped into blocks, typically 512 or 1,024 lines on a side, that share a strip of amplifiers [3]. Modern chips use the open-bitline arrangement [3], which is what made the 6F² cell possible [5]. Around the array sit wordline drivers, decoders, and the spare rows and columns that replace defective ones [9].

Limits and open problems

These circuits are overhead. In a typical commodity DRAM, bitline sense amplifiers take 8% to 15% of the die and local wordline drivers another 5% to 10% [9]. Designers call the cells' share of the die the array efficiency, and work to keep it high [9]. A denser cell also brings bitlines closer together, and modelling of 4F² arrays identifies coupling between neighbouring bitlines as a first-order problem [18].

How one bit is found among billions

A real array has thousands of lines each way; this corner has four rows and five columns. Schematic.

  1. 1The address arrives, and the row decoder works out which row it means.
  2. 2One wordline switches on, opening every cell along that row.
  3. 3Each of those cells shares its charge with its own bitline.
  4. 4A sense amplifier at the foot of every column decides 0 or 1.
  5. 5The column select passes on only the column that was asked for.
  6. 6The bit leaves the chip, and the whole row has been rewritten on the way.

From 6F² to 4F²: the geometry

The job: Fit more cells into the same silicon without making F any smaller.

How it works

F is the smallest feature a layout uses, and cell area is quoted in multiples of F² [5]. Earlier cells took 8F² [17]; an open and folded bitline arrangement proposed in 1994 brought the cell to 6F² [5]. With its wordline buried below the silicon surface, the 6F² cell has carried DRAM from 46 nm to today's 10 nm-class generations [6, 15]. A 4F² cell is 2F by 2F [39], which the industry roadmap calls the practical limit for a cell with one transistor and one capacitor [8]. Going from 6 to 4 removes a third of the area, so 1.5 times as many cells fit in the same array. An early Samsung 4F² design estimated about 30% more gross dies per wafer than 6F² [17].

Limits and open problems

The 1.5× applies to the array alone. Everything outside it stays, so the gain for a whole chip depends on how much of the die is array [9]. Reporting on CXMT's announcement put the expected density gain at 30% to 50%, and noted that early products may adopt 4F² only in part [37].

The same silicon, tiled two ways

F is the smallest feature the layout uses. Both squares are 12 F on a side. Idealised geometry, not a measured chip.

  1. 1Today's cell covers 6F²: three F one way, two F the other.
  2. 2A square 12 F on a side holds 24 of them.
  3. 3A 4F² cell is two F by two F: two thirds of the area.
  4. 4The same square holds 36.
  5. 5That is twelve more cells, one and a half times as many, in the same array area.
  6. 6The circuits around the array do not shrink with it, so the whole chip gains less.

Try it: how much does a whole chip gain?

Idealised model: the cell array shrinks to two thirds and everything else stays the same. Move the slider to change how much of the die is cell array. Not a measurement of any product.

80.0%
of the original die area
+25.0%
more bits in a die of the original size

The vertical-channel transistor

The job: Switch the capacitor on and off from inside a column two F wide.

How it works

In today's 6F² cell the transistor is a saddle-fin device with its wordline buried below the surface [7, 6]. Its source and drain still sit side by side, and that costs area. A 4F² cell stands the channel upright as a pillar, with the bitline buried beneath it and the capacitor on top [10]. The gate can then surround the channel. CXMT's 2023 paper reported a gate-all-around, junctionless vertical transistor with an on/off current ratio above 10⁹ and a sub-threshold swing of 62.5 mV per decade [10], and a companion paper an 8 Gb array at 198 Mbit/mm² [11]. Lower bitline capacitance is a stated benefit of the vertical cell [10].

Who has published

Samsung has published a silicon cell with a back gate shared between neighbouring cells [12], and an oxide-channel vertical transistor that can be built on top of the peripheral circuits [13]. SK hynix has shown a vertical-gate 4F² array integrated over its periphery [14]. Kioxia and Nanya demonstrated a 275 Mbit array with an oxide-channel transistor built on top of the capacitor [16]. CXMT described a vertical surrounded-gate transistor as the basis of its 4F² platform in October 2026 [37, 38].

Limits and open problems

The buried bitline is harder to form than in a conventional cell [10]. Thin, tall silicon structures bend and lean during processing [12]. Tightly packed bitlines couple to one another [18]. These are the problems the published papers set out to solve; none of them reports a product yield.

Standing the transistor on end

Conceptual cross-sections. Real devices differ by maker and are not drawn to scale.

  1. 1In a flat transistor the source, gate and drain sit side by side on the surface.
  2. 2All three need room on the surface, so the cell is wide.
  3. 3Turn the channel upright and it stands on the bitline as a pillar.
  4. 4The gate wraps the pillar, so it controls the channel from every side.
  5. 5The capacitor sits directly on top of the pillar.
  6. 6Everything is stacked in one column, and the cell is narrow.

Printing the pattern

The job: Make lines and pillars finer than lithography can print in one exposure.

How it works

Spacer-based pitch multiplication deposits a thin film on the sides of printed lines, removes the lines and keeps the film: two lines where there was one, at half the pitch [22]. Doing it twice gives a quarter of the printed pitch [22]. CXMT formed the pillars of its vertical transistor by applying double patterning twice, at right angles [10], and states that its fifth-generation platform reaches an 11.95 nm half-pitch with quadruple patterning [36]. Samsung built its 20 nm DRAM without extreme-ultraviolet lithography [20], and at 14 nm used five extreme-ultraviolet layers, cutting process steps by about 20% [21].

Limits and open problems

Lines made this way are never printed directly. Their spacing depends on the width of each printed line and each film, and uneven spacing is a known result [22]. Each extra patterning pass also adds process steps, which is what extreme-ultraviolet lithography reduces [21].

Four lines from one printed line's pitch

Self-aligned quadruple patterning in outline. A real flow has many more deposition, etch and trim steps. Schematic.

  1. 1Lithography prints a set of lines at the finest spacing it can manage.
  2. 2A thin layer is deposited and etched so that it remains only on the sides of each line.
  3. 3The printed lines are removed. Two thin lines stand where each one was.
  4. 4The same trick is repeated on those lines.
  5. 5The result is four times as many lines as were printed, at a quarter of the spacing.
  6. 6No line was printed directly, so an error in any width shifts every line made from it.

The capacitor, and building the logic separately

The job: Keep enough charge in a shrinking footprint, and stop the periphery eating the gain.

How it works

A capacitor's footprint shrinks with the cell, so it grows upward instead. Modern cells use tall, high-aspect-ratio capacitors with a zirconia, alumina, zirconia dielectric between titanium nitride electrodes [19]. The roadmap expects the shape to change from a cylinder to a pillar [8]. Samsung's 20 nm generation gained 21% capacitance at the same cell size from a honeycomb arrangement [20]. CXMT states a capacitor aspect ratio of 45:1 for its fifth-generation platform [36]. The second lever is to stop spending die area on logic: build the cell array on one wafer and the peripheral circuits on another, then bond them, as is already done in 3D NAND flash [23]. SK hynix has demonstrated a 4F² array bonded over its periphery [14], and Samsung has shown the same idea for the existing 6F² cell [24].

Limits and open problems

Tall, narrow structures are sensitive to their etched profile, which changes both leakage and capacitance [19]. Bonding adds alignment and contact steps between wafers [14]. Samsung has also published an alternative that builds oxide transistors over the periphery with no bonding at all [13]. Which route a given product takes is for its maker to state; reporting on CXMT's announcement noted that no specifications were disclosed [38].

Taller capacitors, and logic made separately

Two answers to a shrinking footprint. Whether a given product uses the second is a matter for its maker. Schematic, not to scale.

  1. 1A wide footprint leaves room for a short, broad capacitor.
  2. 2Shrink the footprint and the capacitor must grow taller to hold the same charge.
  3. 3Very tall, very thin structures are hard to etch straight and fill evenly.
  4. 4A second idea: build the cell array on one wafer and the logic around it on another.
  5. 5Then join the two wafers face to face, connection to connection.
  6. 6Each wafer was made with the process that suits it, at the price of a demanding bonding step.

Where DRAM sits in an AI system

The job: Hold models and their working data close enough, and fast enough, for the processors that use them.

How it works

An AI server uses several memories. SRAM inside the chips is the fastest but takes six transistors per bit, so it holds far fewer bits per area than DRAM [34]. NAND flash keeps data without power and stores it as trapped electrons, a different cell altogether [34, 35]. DRAM is the working memory, in two forms. DDR5 devices of 8 Gb to 32 Gb are assembled into modules for the processor [28]. High-bandwidth memory stacks DRAM dies and couples them tightly to the accelerator [29]; the HBM4 standard allows stacks 4 to 16 dies high, with a 2,048-bit interface and up to 2 TB/s [30]. For serving large models the bottleneck is increasingly memory bandwidth rather than arithmetic [31], and the memory each request needs limits how many requests can be batched together [32].

Limits and open problems

Compute has been growing faster than memory: about 3.0× every two years for peak server compute, against 1.6× for DRAM bandwidth [31]. A denser cell adds capacity. It does not close that gap.

Where the memories sit in an AI server

One processor and one accelerator stand in for a whole server. Schematic.

  1. 1SRAM cache sits inside the chips: fastest, and by far the fewest bits.
  2. 2High-bandwidth memory, stacks of DRAM dies, sits right beside the accelerator.
  3. 3DDR5 modules beside the processor are the server's main working memory.
  4. 4NAND flash storage keeps the model when the power is off.
  5. 5To run, a model is loaded from storage, through main memory, into the accelerator's memory.
  6. 6The modules and the stacks are both built from DRAM cells: the cell this report is about.

4F² is not 3D DRAM

The job: Keep two different ideas apart.

How it works

In a 4F² cell the transistor is vertical, but the array is still a single layer of cells. 3D DRAM is a different step: the capacitors are laid horizontally and whole layers of cells are stacked [27], so density rises with the number of layers rather than with a smaller footprint [25]. SK hynix has demonstrated a full chip with five stacked layers [26], and Samsung a 16-layer structure [27]. The roadmap sees no clear path for further scaling beyond the planar cell [8], which is why both routes are being pursued.

Who has published

Samsung calls its version vertically stacked DRAM [25, 27]. SK hynix builds its layers from sacrificial silicon and silicon-germanium films and joins the stack to its logic by hybrid wafer bonding [26].

Limits and open problems

The papers cited here report demonstrations, not products [26, 27].

A smaller footprint is not a taller stack

4F² and 3D DRAM are often confused. Cell counts here are illustrative. Schematic.

  1. 1Today's cells sit side by side in a single layer.
  2. 2A 4F² cell is narrower, so more of them fit in the same width.
  3. 3It is still one layer of cells. The transistor stands upright; the array does not.
  4. 43D DRAM takes the other route: it lays the cells on their side.
  5. 5Then it stacks layer on layer, as NAND flash already does.
  6. 6Both raise density. They are different technologies at different stages.

From an announced architecture to memory you can buy

An architecture is the first of several steps. A server module must also meet the DDR5 device standard [28], be validated by the makers of the platforms it goes into, ship in volume, and cost no more per good bit than what it replaces. Each step needs its own evidence. On the evidence in this report, 4F² has peer-reviewed prototypes from several makers and one reported plan for a server module.

  1. 1

    Disclosed. CXMT described a 4F² platform built on a vertical surrounded-gate transistor at a conference on 10 October 2026, as reported by the trade press [37].

  2. 2

    Prototype. Measured 4F² devices and arrays have been published by CXMT, Samsung, SK hynix, and Kioxia with Nanya [11, 12, 14, 16].

  3. 3

    Samples. No 4F² part number or specification appears in the sources used here; reporting on CXMT noted that none was disclosed [38].

  4. 4

    Qualified. CXMT is reported to plan a DDR5 registered module for servers by the end of 2026 [37, 38]. A plan is not a qualification.

  5. 5

    Volume. Not reported for any 4F² product. CXMT's volume-production statement concerns its fifth-generation platform, which its release does not describe as 4F² [36].

  6. 6

    Economic. No maker has published yield or cost per bit for 4F². Good bits per wafer are dies per wafer × yield × bits per die, and the last two are not public.

From an announced architecture to memory you can buy

Each rung needs its own evidence. A headline usually reports the first. Schematic.

  1. 1Disclosed: the maker describes the architecture in a talk, paper or statement.
  2. 2Prototype: measured devices show that the design works.
  3. 3Samples: a named part with a specification reaches customers.
  4. 4Qualified: server makers validate it on their platforms.
  5. 5Volume: it ships steadily, with yield under control.
  6. 6Economic: the cost of each good bit matches or beats the older cell.

Layout area per bit, in F²

Three generations of DRAM cell [5, 17]. Smaller is denser. Nominal areas, not measured chips.

Whole-die area after moving the array to 4F²

Idealised model: the array shrinks by a third and nothing else changes. Die area as a percentage of the 6F² die, against the share of that die taken by the cell array. Not a measured product.

Claims checked against sources

Figures that circulate widely in this field, each set against its primary source. Where no source supports a figure, this report does not use it.

The claimWhat the source saysVerdict
A 4F² cell is a third smaller than a 6F² cell.Arithmetic on the nominal areas, 4 ÷ 6. Reporting gives the same figure, about 33% [38].Arithmetic: correct, for the cell alone.
4F² gives 50% more memory per chip.The 1.5× holds per array area. Sense amplifiers and drivers take 13% to 25% of the die and do not shrink [9]. Reporting gives a range of 30% to 50% [37].Not established for any product.
Reading a DRAM cell destroys its contents, which must be rewritten.Stated in the original patent and in later circuit descriptions [1, 3].Established physics.
A 4F² cell needs a vertical-channel transistor.The roadmap says so, and the published 4F² cells use one [8, 10, 14, 16].Supported by peer-reviewed work.
Working 4F² arrays exist in silicon.An 8 Gb array from CXMT, a 275 Mbit array from Kioxia and Nanya, and an integrated array from SK hynix [11, 16, 14].Demonstrated in peer-reviewed work.
CXMT's 4F² server memory is shipping.Reported as a plan for the end of 2026, with no specifications disclosed [37, 38].Reported plan, not a shipped product.
CXMT's fifth-generation platform is its 4F² platform.The company's release describes patterning, capacitor and gate advances. It does not mention 4F² [36].Not supported by the company's own release.
CXMT's fifth-generation platform yields at least 50% more dies per wafer.Company release, against its previous platform, normalised to an 8 Gb die [36].Company-reported, not independently verified.
A vertical transistor makes it 3D DRAM.3D DRAM stacks layers of cells; a 4F² array is one layer [25, 27].False: they are different technologies.
Denser DRAM makes AI servers faster.The bottleneck is bandwidth [31], and the interface sets bandwidth [30].Not by itself: it adds capacity, not bandwidth.
The 6F² cell has reached its limit.The roadmap names 4F² as the practical limit of the cell and sees no clear path beyond the planar cell [8]. 6F² is still what modern chips use [7].Supported as a direction, not as a date.
4F² lowers the cost of each bit.No yield or cost figures appear in any source used here.Not established.

Frequently asked questions

What does 4F² mean?

F is the smallest feature a chip's layout uses. A 4F² cell occupies a square two F on each side; today's standard cell occupies 6F². It is a measure of layout area per bit, not the name of a manufacturing node.

Does 4F² mean 50% more memory?

Only for the cell array, and only on paper. A square of silicon holds 1.5 times as many 4F² cells as 6F² cells. The circuits around the array do not shrink, so a whole chip gains less, and no maker has published a measured figure for a product.

Is 4F² the same as 3D DRAM?

No. In a 4F² cell the transistor stands upright, but the memory is still one layer of cells. 3D DRAM stacks several layers of cells on top of one another. Both raise density; they are separate technologies at different stages.

Why does DRAM need refreshing?

Each bit is a small charge on a capacitor, and the charge leaks away. The chip therefore reads and rewrites every cell on a fixed schedule, typically within 64 milliseconds. That is the D in DRAM: dynamic.

Will 4F² make AI models run faster?

Not by itself. A denser cell puts more bits on a chip, which raises the capacity of a module or a memory stack. Speed in serving large models is limited mostly by memory bandwidth, which depends on the interface, not on the cell.

Who is working on 4F² DRAM?

Peer-reviewed demonstrations have come from CXMT, Samsung, SK hynix, and Kioxia with Nanya. In October 2026 CXMT was reported to be planning a server memory module by the end of the year, with no specifications disclosed.

Does Algorythmos design memory chips?

No. Algorythmos builds and operates AI systems: models, pipelines and monitoring. Memory capacity and bandwidth are constraints we plan around, which is why we follow the hardware closely.

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