Does 4F² DRAM Change Your AI Plans? How to Size Memory for the Models You Run

Memory comes first

In October 2026 a DRAM maker described a move to a smaller memory cell, known as 4F², and headlines turned it into 50% more memory. Our evidence report on the 4F² DRAM cell sets out what the geometry gives and what has not been shown: the cell is a third smaller, the whole chip gains less, and no maker has published yield or cost for a product.

The lesson for anyone running AI today is more practical. For serving large models the bottleneck is increasingly memory rather than arithmetic, and a model that does not fit in memory does not run at all. Size the memory first, then choose the hardware.

1. Know which memory you are short of

An AI server has several memories, and they are not interchangeable. Find out which one limits you before buying more of anything.

• Accelerator memory. High-bandwidth memory sits beside the accelerator and holds the model while it runs. If the weights and the working data do not fit here, nothing else matters.
• System memory. DDR5 modules beside the processor hold everything on its way in and out: data being prepared, models being loaded, the services around the model.
• Storage. Flash keeps models and data with the power off. It sets how long a cold start takes.

2. Separate capacity from bandwidth

Capacity is how much fits. Bandwidth is how fast it moves. They run out in different ways, and a denser cell helps only the first.

• Capacity runs out as models, context and batch size grow. The memory each request needs limits how many requests can be served together.
• Bandwidth runs out when processors can compute faster than memory can feed them. Peak server compute has grown about 3.0× every two years, against about 1.6× for DRAM bandwidth.
• The interface sets bandwidth. The HBM4 standard allows up to 2 TB/s across a 2,048-bit interface, and a change to the cell does not alter that.

3. Measure before you size

A sizing taken from a model card is a guess. Measure on the workload you will actually run.

• Peak memory per request, at the context lengths your users really send, not the average.
• Requests served together at your target response time. Raise the batch until memory or response time gives way, and note which gave way first.
• Headroom. Leave room for the next model version and for a traffic peak. A system sized to fit exactly fails on its first busy day.

4. What a denser cell changes, and what it does not

A 4F² cell is a step the industry has taken many times before: more bits in the same silicon. Where it arrives, it is good news for capacity.

• It raises capacity per module or stack, once products built on it are qualified and shipping. The published work so far is prototypes.
• It does not raise bandwidth, and it is not 3D DRAM, which stacks layers of cells and is a separate technology.
• It is not a reason to change plans now. A server module was reported as planned for the end of 2026, with no specifications disclosed.

Where to start

Pick the model that matters most and write down three numbers: the memory it needs per request, how many requests it must serve at once, and the response time you have promised. Measure the system you have against them. The gap between them is the work.

The full analysis, with the source for every figure, nine step-through diagrams and a calculator for the whole-chip gain, is in the evidence report.